This disclosure relates generally to the field of computer memory, and more particular to a non-volatile memory (NVM) device formed with an etch stop layer in the shallow trench isolation (STI) regions.
NVM devices are used in various types of computer memory, for example, flash devices. An NVM device includes a floating gate separated from a control gate by a gate dielectric layer. A major concern in NVM devices is the gate coupling factor. A high gate coupling factor results in good control of the floating gate by the control gate during device operation and increases NVM device performance. The gate coupling factor of a NVM device is dependent on both the capacitance between the control gate and the floating gate, and the capacitance between the floating gate and the substrate. For an increase of 1 volt (V) of the control gate potential, the floating gate potential increases by a factor αCG, which is a factor related to the coupling factor between the floating gate and the control gate. αCG needs to be relatively low to ensure good control of the floating gate by the control gate during device operation. However, capacitance that exists between the floating gate and the device substrate may act to raise αCG. Therefore, in order to raise the gate coupling factor of a NVM device, the capacitance between the control gate and the floating gate needs to be raised and/or the capacitance between the substrate and the floating gate needs to be lowered.
One way to increase the capacitance between the floating gate and the control gate is to decrease the equivalent oxide thickness (EOT) of the gate dielectric located between the floating gate and control gate. However, if the gate dielectric is made too thin, a tunneling current between the floating gate and control gate may arise, leading to the loss of data that is stored in the NVM device. Various floating gate shapes that are used in NVM devices to increase the capacitance between the floating gate and the control gate may also have the effect of increasing the capacitance between the floating gate and the substrate, which results in a relatively low net increase in the gate coupling factor of the device, and hence low increase in NVM device performance.